The recommended power-up sequence is to apply VCC first, followed by VDD, and then the digital inputs. This ensures that the internal voltage regulators are powered up correctly and prevents any potential latch-up conditions.
To minimize noise and EMI, it is recommended to keep the analog and digital grounds separate, use a solid ground plane, and keep the signal traces short and away from the power traces. Additionally, use decoupling capacitors and ferrite beads to filter out high-frequency noise.
The maximum clock frequency that can be used with the PCM1720E is 256 fs (384 kHz), but it is recommended to use a clock frequency of 128 fs (192 kHz) or lower to ensure optimal performance and minimize jitter.
To configure the PCM1720E for Master Clock mode, set the MCLK pin to the desired clock frequency, and set the BCK pin to the desired bit clock frequency. Then, set the WS pin to the desired word select frequency, and set the SDIN pin to the desired serial data input.
The recommended termination scheme for the PCM1720E's digital outputs is to use a 100-ohm differential termination resistor at the receiving end of the transmission line, and to use a 50-ohm series termination resistor at the transmitting end.
PCM1720E datasheet
by Texas Instruments
