PCM1710U datasheet by Texas Instruments

PCM1710U Frequently Asked Questions (FAQs)

• What is the recommended power-up sequence for the PCM1710U?
  The recommended power-up sequence is to apply VCC first, followed by VDD, and then the digital inputs. This ensures that the internal voltage regulators are powered up correctly and prevents any potential latch-up conditions.
• How do I configure the PCM1710U for master clock mode?
  To configure the PCM1710U for master clock mode, set the MCKO pin to a logic high and connect a clock source to the MCKI pin. The device will then generate the master clock signal on the MCKO pin.
• What is the maximum allowed jitter on the master clock input?
  The maximum allowed jitter on the master clock input is 100 ps peak-to-peak. Exceeding this limit may affect the device's performance and cause errors in the audio data.
• How do I implement a mute function using the PCM1710U?
  To implement a mute function, assert the MUTE pin low. This will mute the analog output stages and prevent any audio signals from being output. De-asserting the MUTE pin will restore normal operation.
• What is the recommended layout and routing for the PCM1710U's analog and digital signals?
  It is recommended to keep the analog and digital signals separate and use a multi-layer PCB with a dedicated ground plane. The analog signals should be routed away from the digital signals and the power supply lines to minimize noise and interference.