PCM1702U datasheet by Texas Instruments

PCM1702U Frequently Asked Questions (FAQs)

• What is the recommended power-on sequence for the PCM1702U?
  The recommended power-on sequence is to apply VCC first, followed by VREF, and then the analog and digital inputs. This ensures proper device operation and prevents damage.
• How do I optimize the analog input filter design for the PCM1702U?
  The analog input filter should be designed to reject noise and aliasing. A 3rd-order Butterworth filter with a cutoff frequency of 40 kHz is recommended. The filter should also provide a gain of 1-2 dB to optimize the signal-to-noise ratio.
• What is the recommended clock frequency and jitter tolerance for the PCM1702U?
  The recommended clock frequency is 256 fs (where fs is the sampling frequency). The clock jitter tolerance is ±50 ppm, and the clock amplitude should be between 2.5 V and 5 V.
• How do I handle the PCM1702U's digital output data format?
  The PCM1702U outputs 24-bit data in MSB-first, two's complement format. The data is output on the D0-D23 pins, with D0 being the MSB. The output data rate is equal to the sampling frequency.
• What is the recommended layout and grounding technique for the PCM1702U?
  The PCM1702U requires a solid ground plane and separate analog and digital ground planes. The analog and digital supplies should be decoupled with 10 μF and 100 nF capacitors, respectively. The layout should also minimize noise coupling between analog and digital signals.