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    Part Img PCI9054-AB50PI datasheet by PLX Technology

    • PCI to Local Bus Master I/O Accelerator Chip (PQFP)
    • Original
    • No
    • Unknown
    • Obsolete
    • 3A991.A.2
    • 8542.31.00.01
    • 8542.31.00.00
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    PCI9054-AB50PI datasheet preview

    PCI9054-AB50PI Frequently Asked Questions (FAQs)

    • The maximum power consumption of the PCI9054-AB50PI is 2.5W, with a typical power consumption of 1.5W.
    • The PCI9054-AB50PI can be configured for 64-bit or 32-bit PCI operations through the use of external resistors on the AD[31:0] pins. For 64-bit operation, the resistors should be connected to VCC, and for 32-bit operation, they should be connected to GND.
    • The PCI9054-AB50PI supports clock frequencies up to 66MHz.
    • The PCI9054-AB50PI has a dedicated reset pin (RST#) that can be connected to a reset generator or a power-on reset circuit. The reset pin should be asserted low for at least 10ms to ensure a proper reset.
    • The JTAG interface on the PCI9054-AB50PI is used for boundary scan testing and debugging. It is not intended for programming or configuration of the device.
    Supplyframe Tracking Pixel