PCI1520IPDVEP datasheet by Texas Instruments

PCI1520IPDVEP Frequently Asked Questions (FAQs)

• What is the recommended PCB layout for optimal performance of the PCI1520IPDVEP?
  A 4-layer PCB with a solid ground plane and a separate power plane is recommended. The device should be placed near the connector to minimize signal loss. Decoupling capacitors should be placed close to the device.
• How do I ensure signal integrity on the PCIe lanes?
  Use controlled impedance traces, and maintain a consistent trace width and spacing. Use a common mode filter or a PCIe repeater if signal degradation is observed. Ensure that the PCIe clock is properly terminated.
• What is the recommended power sequencing for the PCI1520IPDVEP?
  Power up the 3.3V supply first, followed by the 1.8V supply. The 1.2V supply can be powered up last. Ensure that the power supplies are stable before applying the PCIe clock.
• How do I troubleshoot PCIe link training issues with the PCI1520IPDVEP?
  Use a PCIe analyzer or a logic analyzer to capture the PCIe signals. Check the PCIe clock frequency and amplitude. Verify that the device is properly configured and that the link partner is compatible.
• What is the maximum cable length supported by the PCI1520IPDVEP?
  The maximum cable length supported is 7 meters for PCIe Gen 1 and 3 meters for PCIe Gen 2. However, the actual cable length may vary depending on the specific application and signal quality.