The recommended power-on sequence is to apply VDD first, followed by VLOGIC, and then the clock signal. This ensures proper initialization of the device.
The self-test feature can be enabled by setting the ST bit in the CTRL_REG1 register. During self-test, the device applies a known acceleration to the sensor and measures the response. The result can be read from the ST_DATA register. Note that self-test should not be performed during normal operation.
The HPF_OUT register provides a high-pass filtered version of the acceleration data. This can be useful for applications that require removal of low-frequency noise or drift.
The interrupt pins can be configured using the INT_CFG register. This register allows selection of the interrupt mode (e.g., pulse or latch), polarity, and the specific interrupt sources (e.g., data ready, overrun, or free-fall).
The maximum sampling rate of the MMA7455LR2 is 1600 Hz, which can be achieved by setting the ODR bit in the CTRL_REG1 register to 11.
MMA7455LR2 datasheet
by Freescale Semiconductor
