The recommended layout and placement for the LTC1740CG involves keeping the input and output capacitors close to the device, using a solid ground plane, and minimizing the length of the traces between the device and the capacitors. A 4-layer board with a solid ground plane is recommended. Refer to the Linear Technology application note AN-72 for more details.
The input and output capacitors should be chosen based on the specific application requirements. A general guideline is to use low-ESR capacitors with a value of 10uF to 22uF for the input capacitor and 22uF to 47uF for the output capacitor. The capacitor voltage rating should be at least 1.5 times the maximum input voltage. Refer to the Linear Technology application note AN-115 for more details.
The maximum input voltage that the LTC1740CG can handle is 36V. However, the device can be operated from a 3.3V or 5V input voltage, and the output voltage can be set to a value between 1.2V and 5V using the feedback resistors.
The output voltage of the LTC1740CG can be adjusted by changing the ratio of the feedback resistors R1 and R2. The output voltage is determined by the equation Vout = 1.2V x (1 + R2/R1). The resistors should be chosen to provide a stable output voltage and to ensure that the output voltage is within the specified range.
The typical efficiency of the LTC1740CG is around 90% to 95% depending on the input voltage, output voltage, and load current. The efficiency can be improved by optimizing the layout, using low-ESR capacitors, and minimizing the voltage drop across the internal switches.
LTC1740CG#PBF datasheet
by Linear Technology
Findchips
