LPC2138FBD64/01 datasheet by NXP Semiconductors

LPC2138FBD64/01 Frequently Asked Questions (FAQs)

• What is the maximum clock frequency of the LPC2138?
  The maximum clock frequency of the LPC2138 is 60 MHz.
• How do I configure the oscillator for the LPC2138?
  The oscillator can be configured using the PLL0CFG and PLL1CFG registers. The PLL0CFG register sets the PLL0 multiplier and the PLL1CFG register sets the PLL1 multiplier.
• What is the purpose of the VPB divider in the LPC2138?
  The VPB divider is used to divide the peripheral clock frequency to generate the clock frequency for the peripherals. It can be configured using the VPBDIV register.
• How do I enable the watchdog timer in the LPC2138?
  The watchdog timer can be enabled by setting the WDTENA bit in the WDTMOD register. The watchdog timer can be configured using the WDTC register.
• What is the purpose of the ARM EmbeddedICE debug interface in the LPC2138?
  The ARM EmbeddedICE debug interface is used for debugging and testing the microcontroller. It provides a way to access the internal state of the microcontroller and to control its execution.