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    Part Img LPC1343FBD48 datasheet by NXP Semiconductors

    • Driving the LPC1300 with Murata resonators
    • Original
    • Yes
    • Unknown
    • Active
    • 3A991.A.2
    • 8542.31.00.01
    • 8542.31.00.00
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    LPC1343FBD48 datasheet preview

    LPC1343FBD48 Frequently Asked Questions (FAQs)

    • The maximum operating frequency of the LPC1343FBD48 is 72 MHz, but it can be overclocked to 80 MHz with some limitations.
    • The boot mode of the LPC1343FBD48 can be configured using the ISP (In-System Programming) pins, specifically the P2[10] and P2[11] pins. The boot mode can be set to either UART, SPI, or I2C.
    • The maximum amount of current that the LPC1343FBD48 can source or sink on its GPIO pins is 4 mA per pin, with a total current limit of 100 mA for all GPIO pins combined.
    • The internal oscillator of the LPC1343FBD48 can be enabled by setting the IRCEN bit in the SYSCONFIG register. The oscillator frequency can be trimmed using the IRCTRIM register.
    • The minimum voltage required for the LPC1343FBD48 to operate is 2.4 V, but it is recommended to operate at a minimum of 2.7 V for optimal performance.
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