The recommended power-on sequence is to apply VDD first, followed by VDDIO, and then the clock signal. This ensures proper initialization of the device.
To configure the LIS35DETR for low-power mode, set the LPEN bit in the CTRL_REG1 register to 1. This reduces the current consumption to approximately 10 μA.
The self-test feature in the LIS35DETR is used to verify the integrity of the sensor and the signal chain. It applies a known stimulus to the sensor and checks the output to ensure it is within expected limits.
The LIS35DETR outputs 16-bit, two's complement data in units of mg (milli-g). The output data is scaled by the sensitivity setting (e.g., ±2g, ±4g, etc.).
The maximum sampling rate of the LIS35DETR is 1.6 kHz, but it can be adjusted by setting the ODR (Output Data Rate) bits in the CTRL_REG1 register.
LIS35DETR datasheet
by STMicroelectronics
