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    Part Img IDT74LVC112APG datasheet by Integrated Device Technology

    • 3.3 V CMOS Dual Negative-Edge-Triggered J-K Flip-Flop with Clear and Preset, 5 V Tolerant I/O
    • Original
    • No
    • Unknown
    • Obsolete
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    IDT74LVC112APG datasheet preview

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