EP9302-CQZ datasheet by Cirrus Logic

EP9302-CQZ Frequently Asked Questions (FAQs)

• What is the recommended power-up sequence for the EP9302-CQZ?
  The recommended power-up sequence is to apply VCC first, followed by VDD, and then VIO. This ensures that the internal voltage regulators are powered up correctly.
• How do I configure the EP9302-CQZ for a specific clock frequency?
  The EP9302-CQZ clock frequency can be configured using the Clock Control Register (CCR). The CCR register allows you to select the clock source, clock frequency, and clock mode. Refer to the datasheet for the specific register settings for your desired clock frequency.
• What is the maximum current draw of the EP9302-CQZ?
  The maximum current draw of the EP9302-CQZ depends on the operating frequency and voltage. According to the datasheet, the maximum current draw is approximately 250mA at 1.8V and 100MHz. However, this value can vary depending on the specific application and operating conditions.
• How do I implement a watchdog timer on the EP9302-CQZ?
  The EP9302-CQZ has a built-in watchdog timer that can be enabled and configured using the Watchdog Timer Control Register (WTCSR). The watchdog timer can be set to reset the processor after a specified timeout period if the timer is not periodically reset by the software.
• What is the purpose of the JTAG interface on the EP9302-CQZ?
  The JTAG (Joint Test Action Group) interface on the EP9302-CQZ is used for debugging and testing purposes. It allows you to access the internal registers and memory of the processor using a JTAG debugger or emulator.