EP9301-IQZ datasheet by Cirrus Logic

EP9301-IQZ Frequently Asked Questions (FAQs)

• What is the recommended power-up sequence for the EP9301-IQZ?
  The recommended power-up sequence is to apply VDDIO first, followed by VDDCORE, and then VDDA. This ensures that the internal voltage regulators are powered up correctly.
• How do I configure the EP9301-IQZ for low-power operation?
  To configure the EP9301-IQZ for low-power operation, set the Power Management Register (PMR) to enable the low-power mode. Additionally, reduce the clock frequency, disable unused peripherals, and adjust the voltage regulators to minimize power consumption.
• What is the maximum clock frequency supported by the EP9301-IQZ?
  The maximum clock frequency supported by the EP9301-IQZ is 200 MHz. However, the actual clock frequency may be limited by the specific application and system design.
• How do I implement a watchdog timer on the EP9301-IQZ?
  The EP9301-IQZ has a built-in watchdog timer that can be enabled and configured through the Watchdog Timer Control Register (WTCR). Set the watchdog timer period and enable the timer by writing to the WTCR register.
• What is the purpose of the JTAG interface on the EP9301-IQZ?
  The JTAG interface on the EP9301-IQZ is used for debugging and testing purposes. It allows for boundary scan, debugging, and programming of the device.