The maximum output current of the DAC7568 is 5mA per channel.
To ensure monotonicity, use a 0.1uF capacitor between the output pin and GND, and a 1kΩ resistor in series with the output pin.
The recommended power-on sequence is to power up VCC first, followed by AVCC, and then the digital interface (SCL and SDA).
To enter power-down mode, set the PD pin low. In power-down mode, the DAC7568's power consumption is reduced, but the output voltage is not guaranteed.
The maximum clock frequency for the I2C interface of the DAC7568 is 400 kHz.
DAC7568ICPW datasheet
by Texas Instruments
