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    Part Img CY7C1470BV25-250AXC datasheet by Cypress Semiconductor

    • 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
    • Original
    • Yes
    • Unknown
    • Transferred
    • 3A991.B.2.A
    • 8542.32.00.41
    • 8542.32.00.40
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    CY7C1470BV25-250AXC datasheet preview

    CY7C1470BV25-250AXC Frequently Asked Questions (FAQs)

    • The CY7C1470BV25-250AXC has an industrial temperature range of -40°C to +85°C, and a commercial temperature range of 0°C to +70°C.
    • The CY7C1470BV25-250AXC has a self-refresh mode that can be enabled by asserting the SREF pin low. This mode reduces power consumption by stopping the clock and disabling the output buffers.
    • The CY7C1470BV25-250AXC supports a maximum clock frequency of 250 MHz.
    • The CY7C1470BV25-250AXC has a built-in data retention feature that retains data for a minimum of 10 years at 85°C. To ensure data retention during power-down, the VCC power supply must be reduced to 0V within 10 ms of the clock signal being stopped.
    • The CY7C1470BV25-250AXC has a read latency of 2.5 clock cycles and a write latency of 2 clock cycles.
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