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    Part Img CY7C1470BV25-200BZXI datasheet by Cypress Semiconductor

    • 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
    • Original
    • Yes
    • Unknown
    • Transferred
    • 3A991.B.2.A
    • 8542.32.00.41
    • 8542.32.00.40
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    CY7C1470BV25-200BZXI datasheet preview

    CY7C1470BV25-200BZXI Frequently Asked Questions (FAQs)

    • The CY7C1470BV25-200BZXI has an operating temperature range of -40°C to +85°C.
    • To implement self-refresh mode, assert the SREF pin low and ensure that the clock is stopped. This will reduce power consumption to a minimum.
    • The CY7C1470BV25-200BZXI supports a maximum clock frequency of 200 MHz.
    • To handle data retention during power-down, use the SLEEP mode by asserting the ZZ pin low. This will retain data and reduce power consumption.
    • The latency for a read operation is 2 clock cycles.
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