CY7C1383D-133AXCT datasheet
by Cypress Semiconductor
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
The maximum operating temperature range for CY7C1383D-133AXCT is 0°C to 70°C (commercial temperature range) and -40°C to 85°C (industrial temperature range).
The CY7C1383D-133AXCT requires a single 3.3V clock signal, which can be generated using an external clock source or a phase-locked loop (PLL) circuit. The clock signal should be connected to the CLK pin.
The maximum data transfer rate for the CY7C1383D-133AXCT is 133 MHz, which translates to a data transfer rate of 1066 MB/s.
During power-up, the CY7C1383D-133AXCT requires a controlled power-up sequence to ensure proper initialization. The VDD and VDDQ pins should be powered up simultaneously, and the clock signal should be applied after the power-up sequence is complete. During power-down, the clock signal should be stopped before powering down the VDD and VDDQ pins.
The latency for the CY7C1383D-133AXCT is 2.5 clock cycles for read operations and 1 clock cycle for write operations.
