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    Part Img CY7C1381D-133AXC datasheet by Cypress Semiconductor

    • 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
    • Original
    • Yes
    • Yes
    • Obsolete
    • 3A991.B.2.A
    • 8542.32.00.41
    • 8542.32.00.40
    • Find it at Findchips.com

    CY7C1381D-133AXC datasheet preview

    CY7C1381D-133AXC Frequently Asked Questions (FAQs)

    • The CY7C1381D-133AXC has an operating temperature range of 0°C to 70°C (commercial temperature range) and -40°C to 85°C (industrial temperature range).
    • To implement self-refresh mode, assert the SREF input low and ensure that the clock is stopped. This will reduce power consumption to a minimum. However, note that the device will not retain data in self-refresh mode.
    • The CY7C1381D-133AXC supports a maximum clock frequency of 133 MHz.
    • To handle data bus turnaround times, ensure that the data bus is in a high-impedance state (tri-stated) during the turnaround period. This can be achieved by asserting the OE# (output enable) signal low.
    • The ZZ pin is used to put the device in a sleep mode, which reduces power consumption. When the ZZ pin is asserted low, the device enters a low-power state, and all internal clocks are stopped.
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