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    Part Img CY7C1381D-100AXC datasheet by Cypress Semiconductor

    • 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
    • Original
    • Yes
    • Yes
    • Obsolete
    • 3A991.B.2.A
    • 8542.32.00.41
    • 8542.32.00.40
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    CY7C1381D-100AXC datasheet preview

    CY7C1381D-100AXC Frequently Asked Questions (FAQs)

    • The maximum frequency of operation for the CY7C1381D-100AXC is 100 MHz.
    • The latency of the CY7C1381D-100AXC is 2.5 clock cycles for read operations and 1 clock cycle for write operations.
    • The burst length of the CY7C1381D-100AXC is 4 beats.
    • Yes, the CY7C1381D-100AXC supports byte writes.
    • The power consumption of the CY7C1381D-100AXC is typically 1.2W at 100 MHz operation.
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