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    CY7C1380D-167AXCT datasheet by Cypress Semiconductor

    • 18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
    • Original
    • Yes
    • Yes
    • Obsolete
    • 3A991.B.2.A
    • 8542.32.00.41
    • 8542.32.00.40
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    CY7C1380D-167AXCT datasheet preview

    CY7C1380D-167AXCT Frequently Asked Questions (FAQs)

    • The maximum operating temperature range for CY7C1380D-167AXCT is 0°C to 70°C (commercial temperature range) and -40°C to 85°C (industrial temperature range).
    • To implement self-refresh mode, assert the Chip Select (CS) signal low and then assert the Clock Enable (CKE) signal low. The device will then enter self-refresh mode, reducing power consumption.
    • The maximum clock frequency supported by CY7C1380D-167AXCT is 167 MHz.
    • To handle data integrity during power-down or power-up sequences, ensure that the device is in a quiescent state (no clock or data activity) before powering down or up. Also, use the Power-On Reset (POR) circuit to ensure a clean reset of the device during power-up.
    • The latency for read and write operations in CY7C1380D-167AXCT is 2.5 clock cycles for read operations and 1 clock cycle for write operations.
    Supplyframe Tracking Pixel