CY7C1372DV25-167AXCT datasheet by Cypress Semiconductor

Description 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 2.4 to 2.6 V
Datasheet Type Original
RoHS Yes
Pb Free Yes
Lifecycle Obsolete
ECCN 3A991.B.2.A
HTS Code 8542.32.00.41
Schedule B 8542.32.00.40
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CY7C1372DV25-167AXC

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