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    Part Img CY7C1370D-167BZXC datasheet by Cypress Semiconductor

    • 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
    • Original
    • Yes
    • Yes
    • Obsolete
    • 3A991.B.2.A
    • 8542.32.00.41
    • 8542.32.00.40
    • Find it at Findchips.com

    CY7C1370D-167BZXC datasheet preview

    CY7C1370D-167BZXC Frequently Asked Questions (FAQs)

    • The CY7C1370D-167BZXC has an operating temperature range of 0°C to 70°C (commercial grade) and -40°C to 85°C (industrial grade).
    • To implement self-refresh mode, assert the SREF pin low and ensure that the clock is stopped. This will reduce power consumption to a minimum.
    • The CY7C1370D-167BZXC supports a maximum clock frequency of 167 MHz.
    • To handle data bus turnaround times, ensure that the data bus is tri-stated before switching between read and write operations. This can be done by inserting a small delay between operations.
    • The ZZ pin is a sleep mode pin that can be used to reduce power consumption. To use it, assert the ZZ pin low to enter sleep mode, and assert it high to exit sleep mode.
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