CY7C1361C-100AXE datasheet
by Cypress Semiconductor
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
The CY7C1361C-100AXE has an operating temperature range of 0°C to 70°C (commercial grade) and -40°C to 85°C (industrial grade).
To implement self-refresh mode, assert the CE# pin low, and then toggle the CLK pin to initiate the self-refresh cycle. The device will automatically refresh the DRAM array, reducing power consumption.
The CY7C1361C-100AXE supports a maximum clock frequency of 100 MHz.
To ensure data bus turnaround times, insert a minimum of one clock cycle between read and write operations. This allows the device to complete any pending operations and ensure data integrity.
The ZZ pin is a sleep mode input that allows the device to enter a low-power state. To use it, assert the ZZ pin low to put the device in sleep mode, reducing power consumption.