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    Part Img CY7C1354C-166AXI datasheet by Cypress Semiconductor

    • 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
    • Original
    • Yes
    • Yes
    • Transferred
    • 3A991.B.2.A
    • 8542.32.00.41
    • 8542.32.00.40
    • Find it at Findchips.com

    CY7C1354C-166AXI datasheet preview

    CY7C1354C-166AXI Frequently Asked Questions (FAQs)

    • The maximum frequency of operation for the CY7C1354C-166AXI is 166 MHz.
    • The latency of the CY7C1354C-166AXI is 2.5 clock cycles for read operations and 1 clock cycle for write operations.
    • The burst length of the CY7C1354C-166AXI is 4 beats.
    • Yes, the CY7C1354C-166AXI supports byte writes.
    • The power consumption of the CY7C1354C-166AXI is typically 1.2W at 166 MHz.
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