CY7C1328G-133AXIT datasheet by Cypress Semiconductor

Description 4-Mbit (256K x 18) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 4 Mb; Organization: 256Kb x 18; Vcc (V): 3.1 to 3.6 V
Datasheet Type Original
RoHS Yes
Pb Free Yes
Lifecycle Obsolete
ECCN 3A991.B.2.A
HTS Code 8542.32.00.41
Schedule B 8542.32.00.40
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CY7C1328G-133AXIT datasheet preview Download Datasheet