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    Part Img CY7B991V-5JI datasheet by Cypress Semiconductor

    • Low Voltage Programmable Skew Clock Buffer
    • Original
    • No
    • No
    • Obsolete
    • 8542.39.00.01
    • 8542.39.00.00
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    CY7B991V-5JI datasheet preview

    CY7B991V-5JI Frequently Asked Questions (FAQs)

    • The CY7B991V-5JI can operate at clock frequencies up to 200 MHz.
    • To implement a FIFO buffer, connect the input data to the SI (Serial Input) pin, and the output data to the SO (Serial Output) pin. Use the clock input (CLK) to synchronize the data transfer. You can also use the CY7B991V-5JI's built-in FIFO mode to simplify the implementation.
    • The CY7B991V-5JI has a maximum data transfer rate of 400 Mbps.
    • Yes, the CY7B991V-5JI can be used as a UART. It has a built-in UART mode that supports asynchronous data transfer with a maximum baud rate of 115.2 kbps.
    • The CY7B991V-5JI can be reset by asserting the RESET pin low for at least 10 ns. This will reset the device to its default state.
    Supplyframe Tracking Pixel