The recommended power-up sequence is to apply VDD first, followed by VCC, and then the clock signal. This ensures proper initialization and prevents damage to the device.
To optimize the analog input impedance, use a series resistor (Rs) and a capacitor (Cs) in parallel with the input signal. The values of Rs and Cs depend on the specific application and input signal characteristics. A good starting point is Rs = 1 kΩ and Cs = 10 nF.
The maximum input signal amplitude for the CS5366 is ±2.5 Vpp (peak-to-peak) for a 3.3 V supply voltage. Exceeding this limit may result in distortion or damage to the device.
The CS5366 can be configured for differential or single-ended input modes by setting the appropriate pins (IN1P, IN1N, IN2P, and IN2N) and using the correct input termination resistors. Refer to the datasheet and application notes for specific configuration details.
The typical latency of the CS5366 is around 10-15 clock cycles, depending on the specific configuration and clock frequency. This latency is due to the internal pipeline architecture and can be affected by the clock frequency and other system parameters.
CS5366-CQZR datasheet
by Cirrus Logic
Findchips
Findchips