The recommended power-up sequence is to apply VCC first, followed by VDD, and then the clock signal. This ensures proper initialization and prevents damage to the device.
To configure the CS4392-KZ for master clock mode, set the MCLK pin to the desired clock frequency, and then set the BCK pin to the desired bit clock frequency. The device will then generate the LRCK signal internally.
The maximum allowed jitter on the MCLK input is 500 ps peak-to-peak. Exceeding this limit may result in errors or unstable operation.
Yes, the CS4392-KZ can be used with separate analog and digital power supplies. However, it's essential to ensure that the analog power supply is well-filtered and decoupled from the digital power supply to prevent noise coupling and interference.
To optimize the CS4392-KZ's performance for low-power applications, reduce the clock frequency, use the lowest possible voltage supply, and enable the power-down mode when not in use. Additionally, consider using a lower-power variant of the device, such as the CS4392-KZ-105.
CS4392-KZ datasheet
by Cirrus Logic
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