CDCM1802RGTR datasheet by Texas Instruments

CDCM1802RGTR Frequently Asked Questions (FAQs)

• What is the recommended PCB layout for the CDCM1802RGTR?
  Texas Instruments recommends a 4-layer PCB with a solid ground plane and a separate power plane for the VCC and VDD pins. The clock input traces should be kept short and away from noisy signals.
• How do I ensure the CDCM1802RGTR is properly bypassed?
  Use a 0.1uF ceramic capacitor between VCC and GND, and a 10uF electrolytic capacitor between VCC and GND, both placed as close to the device as possible.
• What is the maximum clock frequency that the CDCM1802RGTR can handle?
  The CDCM1802RGTR can handle clock frequencies up to 180 MHz, but the maximum frequency may be limited by the specific application and PCB layout.
• How do I configure the CDCM1802RGTR for a specific clock output frequency?
  The CDCM1802RGTR has a programmable clock divider that can be configured using the SEL0-SEL2 pins. Consult the datasheet for specific configuration options and equations to calculate the desired output frequency.
• What is the power consumption of the CDCM1802RGTR?
  The power consumption of the CDCM1802RGTR depends on the clock frequency and output load. Typical power consumption is around 20-30mA at 3.3V and 100MHz clock frequency.