CDCLVD110AVFR datasheet by Texas Instruments

Description CDCLVD110 - 1-to-10 LVDS Clock Buffer up to 1100MHz with Minimum Skew for Clock Distribution 32-LQFP -40 to 85
Datasheet Type Original
RoHS Yes
Pb Free Yes
Lifecycle Active
ECCN EAR99
HTS Code 8542.39.00.01
Schedule B 8542.39.00.00
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CDCLVD110AVFR datasheet preview

The recommended operating voltage range for the CDCLVD110AVFR is 1.71V to 1.89V.
To ensure proper power supply, connect the VCC pin to a stable 1.8V power source, and decouple it with a 0.1uF capacitor to ground.
The CDCLVD110AVFR supports clock frequencies up to 110 MHz.
To configure the CDCLVD110AVFR for LVDS output, connect the LVDS_EN pin to VCC, and ensure the output is terminated with a 100-ohm differential load.
The typical power consumption of the CDCLVD110AVFR is around 15mA at 1.8V supply voltage.

CDCLVD110AVFR datasheet preview Download Datasheet