CDCE906PW datasheet by Texas Instruments

CDCE906PW Frequently Asked Questions (FAQs)

• What is the recommended power-up sequence for the CDCE906PW?
  The recommended power-up sequence is to apply VCC first, followed by VDD, and then the input clock signal. This ensures proper device operation and prevents latch-up.
• How do I optimize the loop bandwidth of the CDCE906PW for my specific application?
  The loop bandwidth can be optimized by adjusting the values of the RFB and CFB components. A higher RFB value increases the loop bandwidth, while a higher CFB value decreases it. The optimal values depend on the specific application requirements and can be determined through simulation and experimentation.
• What is the maximum input clock frequency that the CDCE906PW can handle?
  The maximum input clock frequency that the CDCE906PW can handle is 250 MHz. However, the device can also be used with higher input frequencies by using an external divider or a frequency multiplier.
• How do I ensure that the CDCE906PW is properly bypassed and decoupled?
  Proper bypassing and decoupling of the CDCE906PW involves placing 0.1 μF and 10 μF capacitors between VCC and GND, and VDD and GND, respectively. Additionally, a 1 μF capacitor should be placed between the output of the voltage regulator and the input of the CDCE906PW.
• What is the maximum output frequency that the CDCE906PW can generate?
  The maximum output frequency that the CDCE906PW can generate is 1.5 GHz. However, the actual output frequency range depends on the input clock frequency, the PLL multiplication factor, and the output divider ratio.