The recommended power-up sequence is to apply VCC first, followed by VDD, and then the clock signal. This ensures proper initialization and prevents potential latch-up conditions.
To optimize the clock signal, ensure a clean and stable clock source with a rise time of <1ns and a fall time of <1ns. Also, use a clock frequency that is within the specified range (25MHz to 200MHz) and avoid clock frequencies that are close to the PLL's natural frequency (around 100MHz).
The CDC7005RGZR can tolerate up to 1ps of input clock jitter. Exceeding this limit may affect the device's performance and cause errors.
Configure the device by setting the appropriate values for the PLL's multiplication factor (M) and division factor (N) using the device's control registers. Refer to the datasheet for the calculation formulas and examples.
The built-in loop filter helps to filter out high-frequency noise and improve the PLL's stability. It is recommended to use the internal loop filter, but it can be bypassed if an external filter is required.
CDC7005RGZR datasheet
by Texas Instruments
