CDC328AD datasheet by Texas Instruments

CDC328AD Frequently Asked Questions (FAQs)

• What is the recommended power-up sequence for the CDC328AD?
  The recommended power-up sequence is to apply VCC before applying CLKIN. This ensures that the internal phase-locked loop (PLL) is properly initialized.
• How do I optimize the CDC328AD for low jitter performance?
  To optimize for low jitter performance, use a high-quality clock source, minimize the length of the clock signal traces, and use a low-jitter PLL loop filter. Additionally, ensure that the power supply is well-regulated and decoupled.
• What is the maximum frequency of operation for the CDC328AD?
  The maximum frequency of operation for the CDC328AD is 200 MHz. However, the actual maximum frequency may be limited by the quality of the clock source, the PCB layout, and the system noise environment.
• How do I configure the CDC328AD for a specific clock frequency?
  The CDC328AD can be configured for a specific clock frequency by selecting the appropriate values for the R and C components in the PLL loop filter. The datasheet provides a formula for calculating these values based on the desired clock frequency.
• What is the purpose of the VREF pin on the CDC328AD?
  The VREF pin is used to set the internal voltage reference for the PLL. It should be connected to a stable voltage source, typically VCC/2, to ensure proper PLL operation.