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    Part Img CD4043BDR datasheet by Texas Instruments

    • CMOS Quad NOR R/S Latch with 3-State Outputs
    • Original
    • Yes
    • Yes
    • Active
    • EAR99
    • 8542.39.00.01
    • 8542.39.00.00
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    CD4043BDR datasheet preview

    CD4043BDR Frequently Asked Questions (FAQs)

    • The recommended operating voltage range for the CD4043BDR is 4.5V to 15.5V.
    • To ensure proper power-on and power-off, the CD4043BDR requires a monotonic power supply ramp-up and ramp-down. A minimum of 1ms is recommended for power-on and power-off times.
    • The CD4043BDR can handle clock frequencies up to 10MHz.
    • The output enable (OE) pin should be tied to VCC or GND through a 1kΩ to 10kΩ resistor to ensure proper operation. Leaving the OE pin floating can cause unpredictable behavior.
    • The master reset (MR) pin is used to asynchronously reset the CD4043BDR. It should be tied to VCC through a 1kΩ to 10kΩ resistor to ensure proper operation.
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