The recommended power-up sequence is to apply the analog power supply (AVDD) first, followed by the digital power supply (DVDD), and then the clock signal. This ensures proper initialization of the device.
To optimize performance, ensure that the analog input signals are properly filtered and terminated, and that the device is operated within the recommended operating conditions. Additionally, use a low-noise power supply, and consider using a separate analog ground plane to reduce digital noise coupling.
The maximum clock frequency is 125 MHz, but it's recommended to use a clock frequency of 100 MHz or less to ensure reliable operation and minimize jitter.
The ADS5273IPFP can be configured for differential or single-ended input operation through the use of external resistors and capacitors. For differential input operation, connect the input signals to the INP and INM pins, and use a differential termination resistor. For single-ended input operation, connect the input signal to the INP pin and use a single-ended termination resistor.
The latency of the ADS5273IPFP is approximately 10 clock cycles, which means that there is a delay of 10 clock cycles between the input signal and the corresponding digital output. This latency should be taken into account when designing the system, especially in applications that require real-time processing or synchronization.
ADS5273IPFP datasheet
by Texas Instruments
