Texas Instruments provides a layout and routing guide in the ADC34J24IRGZT Evaluation Module User's Guide (SLAU445) that should be followed to achieve optimal performance. Additionally, it is recommended to keep the analog and digital signals separate, use a solid ground plane, and minimize the length of the analog input traces.
The ADC34J24IRGZT requires a low-jitter clock signal with a frequency range of 100 MHz to 1.2 GHz. The clock signal should be driven differentially into the CLK+ and CLK- pins. A clock source with a jitter of less than 100 fs RMS is recommended. Additionally, the clock signal should be synchronized with the data capture to ensure proper data conversion.
The recommended power-up sequence is to apply the analog power supply (AVDD) first, followed by the digital power supply (DVDD). The ADC34J24IRGZT should be powered up in the following order: AVDD, DVDD, and then the clock signal. For power-down mode, the clock signal should be stopped, followed by the digital power supply (DVDD), and then the analog power supply (AVDD).
The ADC34J24IRGZT has an internal calibration mode that can be enabled through the SPI interface. The calibration options include offset calibration, gain calibration, and linearity calibration. The calibration process involves applying a known input signal and adjusting the internal calibration registers to achieve optimal performance.
The ADC34J24IRGZT can handle input frequencies up to 1.5 GHz. However, the maximum input frequency that can be converted with optimal SNR is dependent on the sampling rate and the analog input bandwidth. As the input frequency approaches the Nyquist frequency, the SNR will degrade due to the increased noise and distortion.
ADC34J24IRGZT datasheet
by Texas Instruments
