The recommended input impedance for the ADC108S102CIMT is 1 kΩ to 10 kΩ. This ensures that the input signal is properly terminated and minimizes signal reflections.
The ADC108S102CIMT requires a clock signal with a frequency range of 1 MHz to 50 MHz. The clock signal should be a clean, low-jitter signal with a duty cycle of 40% to 60%. It's recommended to use a dedicated clock source or a clock buffer to ensure a stable clock signal.
The maximum sampling rate of the ADC108S102CIMT is 1 MSPS (million samples per second). However, the actual sampling rate may be limited by the clock frequency, input signal bandwidth, and system noise.
The ADC108S102CIMT does not require calibration. It has an internal calibration circuit that ensures accurate conversions. However, it's recommended to perform a system-level calibration to account for any system-level errors or offsets.
The power consumption of the ADC108S102CIMT depends on the operating frequency and supply voltage. At a clock frequency of 10 MHz and a supply voltage of 3.3 V, the typical power consumption is around 15 mW. However, this value can vary depending on the specific application and operating conditions.
ADC108S102CIMT datasheet
by Texas Instruments
