The recommended input impedance for the ADC104S101 is 1 kΩ to 10 kΩ. This ensures proper signal attenuation and filtering to achieve optimal performance.
The ADC104S101 requires a clock signal with a frequency range of 1 MHz to 50 MHz. It's recommended to use a clock signal with a 50% duty cycle and a low jitter to ensure accurate conversions.
The maximum sampling rate of the ADC104S101 is 200 kSPS (kilosamples per second). However, the actual sampling rate may vary depending on the clock frequency and the conversion mode.
The ADC104S101 can be configured for differential or pseudo-differential input modes by setting the corresponding pins (AINP and AINN) and using the appropriate input configuration registers. Refer to the datasheet for specific pin configurations and register settings.
The power consumption of the ADC104S101 varies depending on the operating mode and clock frequency. Typically, it consumes around 15 mW at 1 MSPS and 3.3 V supply voltage. Refer to the datasheet for detailed power consumption specifications.
ADC104S101CIMMX/NOPB datasheet
by Texas Instruments
