DSA00202224.pdf by Cypress Semiconductor

Partial File Text CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Functional Description 72-Mbit density (8M x 8, 8M x
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RoHS Unknown
Pb Free Unknown
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CY7C1546V18 CY7C1548V18 CY7C1550V18 CY7C1557V18