This site uses third-party website tracking technologies to provide and continually improve our services, and to display advertisements according to users' interests. I agree and may revoke or change my consent at any time with effect for the future.
PRELIMINARY
Delta39KTM ISRTM CPLD Family
CPLDs at FPGA DensitiesTM
1
Features
·High density -- 15K to 350K usable gates -- 256 to 5376 macrocells -- 92 to 520 maximum I/O pins -- 12 Dedicat
