DSA00165017.pdf by Cypress Semiconductor
- PRELIMINARY CY7C1557V18 CY7C1548V18 CY7C1550V18 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features · 72-Mbit density (8M x 9, 4M x 18, 2M x 36) · 300 MHz to 375 M
- Original
- Unknown
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