DSA00165043.pdf by Cypress Semiconductor
- PRELIMINARY CY7C1257V18 CY7C1248V18 CY7C1250V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features · 36-Mbit density (4M x 9, 2M x 18, 1M x 36) · 300 MHz to 375 M
- Original
- Unknown
- Unknown
- Unknown
-
Powered by
Findchips
