DSA00165047.pdf by Cypress Semiconductor

Partial File Text PRELIMINARY CY7C1277V18 CY7C1268V18 CY7C1270V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features · 36-Mbit density (4M x 9, 2M x 18, 1M x 36) · 300 MHz to 400 M
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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