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PRELIMINARY
CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18
36-Mbit DDR-II SRAM 2-Word Burst Architecture
Features
· 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) · 300-MHz clock for
