DSA00166622.pdf by Cypress Semiconductor
- CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 300 MHz to 375
- Original
- Unknown
- Unknown
- Unknown
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