DSA00167734.pdf
by Cypress Semiconductor
-
PRELIMINARY
CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
Features
Configurations
With Read Cycle Late
-
Original
-
Unknown
-
Unknown
-
Unknown
-