DSA00167825.pdf by Cypress Semiconductor

Partial File Text CY7C15632KV18 72-Mbit QDR®II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations With Read Cycle Latency of 2.5 cycles: CY7C15632KV18 4M x 18 Separate Indep
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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CY7C15632KV18-400BZXI CY7C15632KV18-550BZC

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