DSA00186788.pdf by PhaseLink

Partial File Text PLL202-107 Programmable Clock Generator for SIS 645/650 P4 Chip Sets PIN CONFIGURATION FEATURES · · · · · · · · · · · BLOCK DIAGRAM XIN XOUT VDD_CPU CPU_STOP# CPUT (0:1)
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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48MHZ PLL202-107 sis 648 SIS 650 ZCLK0

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