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Partial File Text LS TTL DN74LS Series DN74LS76 D N 74LS76 D ^ 74^ 7^ Dual J-K F lip -F lo p s (with S e t and Reset) Description D N 7 4 L S 7 6 contains tw o negative-edge triggered J-K flip-flop circuits,
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IC 74LS76 j-k flip flop 74ls76 logic ic 74LS76 pin diagram