DSAFRAZ0011193.pdf by Integrated Device Technology

Partial File Text ® IDT 36-Bit SyncFIFOs DESCRIPTION: IDT's family of 36-bit SyncFIFOs provides data buffering for buses up to 36-bits wide. This bus width, together with a 67 MHz maximum clock rate, permits a
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024 unidirectional 120-PIN 128-PIN PN120-1 to18-bit